The present invention relates to a variable resistor circuit and a digital-to-analog converter in which the variable resistor circuit is employed as a feedback resistor. More specifically, the present invention relates to a variable resistor circuit of digital control which is controlled by an output signal of a counter and a zero detect mute circuit of an output circuit section in a digital-to-analog converter in which a sigma-delta modulator is employed.
Conventionally, an output circuit section of a digital-to-analog converter (D/A converter) in which a sigma-delta modulator is employed is constituted, for example, as shown in FIG. 1. A multibit digital signal is inputted to a sigma-delta modulator 11. One bit output signal NRZ of this sigma-delta modulator 11 is supplied to one side input terminal of an AND gate 12 and is inverted so as to be supplied to one side input terminal of a NAND gate 13. A clock signal CK is supplied to the other input terminal of the AND gate 12, and the clock signal CK is supplied to the other input terminal of the NAND gate 13.
An output signal RZ of the AND gate 12 is supplied to one end of a resistor 15 via an inverter 14, and an output signal RZn of the NAND gate 13 is supplied to one end of a resistor 17 via an inverter 16. The other ends of the resistors 15, 17 are connected to one end of a resistor 18, and the other end of the resistor 18 is connected to one end of a resistor 19. A capacitor 20 is connected between the one end of the resistor 18 and ground point GND, and a capacitor 21 is connected between the other end of the resistor 18 and ground point GND. The other end of the resistor 19 is connected to the inverting input terminal (-) of an operational amplifier (op-amp) 22, and the non-inverting input terminal (+) of this op-amp 22 is connected to ground point GND.
A capacitor 23 and a resistor 24 are connected in parallel between the output terminal and the inverting input terminal (-) of the op-amp 22 so that an output signal PRZ is feedback to the inverting input terminal (-).
The 1-bit output signal NRZ outputted from the sigma-delta modulator 11 typically becomes that as shown in a timing chart of FIG. 2. The output signal RZ of the AND gate 12 is an AND (logical product) of the 1-bit output signal NRZ and the clock signal CK, and the output signal RZn of the NAND gate 13 is a NAND (NOT-AND) of the inverted signal of the 1-bit output signal NRZ and the clock signal CK. The output signal PRZ of the D/A converter has a waveform made by synthesizing the output signal RZ of the AND gate 12 and the output signal RZn of the NAND gate 13.
In the D/A converter, there are many cases in which a function (hereafter, zero detect mute function) is required in which it is detected that an input digital signal is zero data for a constant period of time and the output is fixed to a constant DC value (typically, mid electric potential). That is, generally, there are many cases in which a large scale of digital circuit exists on the same chip or the same board in a D/A converter, and a large amount of unnecessary radiation bursts in on the D/A converter from the digital circuit via space or a power supply line as a noise. In the sigma-delta modulator 11, even when the zero data are inputted, the 1-bit output signal does not become the DC value but becomes a waveform containing an extremely high frequency noise due to a requantization noise. Thus, even though nothing is essentially supposed to be outputted when an inputted digital signal is zero data, there are many cases in which an unpleasant sound is emitted and/or a poor value is outputted at measurement of a signal-to-noise ratio due to the noise.
In order to prevent this from occurring, when zero data continue for a constant period of time (typically, approximately 100 msec), a zero detect mute function in which said condition is detected and an analog signal of the D/A converter is fixed to a ground potential or reference potential is employed. Since the reference potential is typically decoupled by a capacitor with a large amount of capacitance, mixing of noise is small, thereby preventing an unpleasant sound from being emitted and/or a measured value of an S/N ratio from becoming poor by the mute function.
FIG. 3 shows a structural example of an output circuit section of a conventional D/A converter with the zero detect mute function described above. This output circuit section performs on/off control for an output signal MUTE of a zero detect circuit 26 by connecting an analog switch circuit 25 between the output terminal and the inverting input terminal (-) of the op-amp 22 in the circuit shown in FIG. 1 mentioned above. A multibit digital signal is inputted to the zero detect circuit 26, and in this zero detect circuit 26, it is decided whether or not the feedback resistor 24 of the op-amp 22 is short-circuited, in other words, mute on/off is decided.
In this type of circuit structure, when it is detected that zero data continues for a constant period of time as a multibit digital signal by means of the zero detect mute circuit 26, by turning the analog switch circuit 25 on, the feedback resistor (resistor 24) of the op-amp 22 is short-circuited, thereby preventing an unpleasant sound from being emitted and/or a measured value of an S/N ratio from becoming poor by noise.
However, in the circuit structure described above, there is a big problem in performing the on/off of the mute by the zero detection. That is, click sounds occur at the time of mute on/off. Although this click sound occurs since the DC values at the times of mute ON and mute OFF are different, the causes are various as described below.
First, there is a click sound due to a digital DC offset. Typically, in the D/A converter with the zero detect mute function, in order to prevent the problem that is peculiar to the sigma-delta modulator wherein a fixed pattern occurs at the time of inputting the zero data, thereby causing a unpleasant beat sound, there are many cases in which an adder 27 is provided in the input terminal of the sigma-delta modulator 11 as shown in FIG. 4 so that a digital DC offset as shown in FIG. 5 is added to the input signal of the sigma-delta modulator 11 in advance. With this, as a matter of course, an analog DC offset corresponding to the input digital DC offset is outputted, and thus the click sound occurs at the time of mute on/off.
Therefore, a method is adopted in which an adder 28 is provided between the other ends of the resistors 15, 17 and the one end of the resistor 18 so that an analog DC offset for canceling the digital DC offset is added. However, the DC offset cannot be cancelled completely under the influence of element accuracy or element unevenness or the like, whereby a little DC offset remains.
Second, there is a DC offset due to waveform blunting or element unevenness of the D/A converter (hereafter DAC), in other words, there is a DC error as a DAC.
Lastly, there is an equivalent input DC offset of the op-amp 22. As shown in FIG. 6, when the feedback resistor 24 is short-circuited by the analog switch circuit 25 so as to perform the mute, in the op-amp 22 having the equivalent input DC offset, that is, EOS, this EOS's DC displacement (2EOS at the time of mute off, EOS at the time of mute ON) occurs at the mute on/off so as to become a click sound.
Although the causes described above may be made reduced by a device in a circuit structure, an improvement in element accuracy, a restraint in element unevenness, or the like, they cannot be eliminated completely. That is, a little DC displacement inevitably occurs at the mute on/off, and a click sound occurs.
Therefore, in order to reduce the click sound as much as possible, a technique has been devised wherein the feedback resistor 24 itself is made a variable resistor as a substitute for the analog switch circuit 25 in the circuit shown in FIGS. 3 and 4 so as to make the click sound small by increasing or decreasing the amount of resistance step by step.
That is, when it is supposed that a potential difference of EM in the mute on/off occurs, if on/off is performed at one time by the analog switch circuit 25, a step-shaped waveform occurs as shown FIG. 7, emitting a ringing click sound. However, when the voltage is stepwise changed as shown in FIG. 8, the click sound small in the sense of hearing. In this case of FIG. 8, the voltage is made small by 15 steps. Further, when the number of steps are increased so as to smoothly change the voltage as shown in FIG. 9, the click sound can be made smaller as a matter of course.
FIG. 10 shows a structural example of the output circuit section of the DAC having the zero detect mute function to make the click sound small. The multibit digital signal is inputted to the sigma-delta modulator 11 and the zero detect circuit 26. A digital output of an m level outputted from the delta-sigma modulator 11 is supplied to a DAC 31 of an m level, and an analog output from this DAC 31 is supplied to the inverting input terminal (-) of the op-amp 22 via resistors 32, 18, 19. Here, the output level of the sigma-delta modulator 11 is generally a value of approximately m=2-15. The capacitor 20 is connected between the node of the resistors 32, 18 and ground point GND, and the capacitor 21 is connected between the node of the resistors 18, 19 and ground point GND.
A reference potential VREF is applied to the non-inverting input terminal (+) of the op-amp 22. This reference potential VREF is generated by resistors 33, 34 connected in series between power supply VDD and ground point GND and a capacitor 35 connected between the node of these resistors 33, 34 and ground point GND.
The capacitor 24 and a variable resistor circuit 36 are connected in parallel between the output terminal and the inverting input terminal (-) of the op-amp 22. The variable resistor circuit 36 acts as a feedback resistor of the op-amp 22, and its resistance changes stepwise 0 to (2.sup.n -1)r.
The output signal of the zero detect circuit 26 is supplied to an n-bit up/down (U/D) counter 37. The n-bit discrete value outputted from the counter 37 is supplied to a decoder 38. This decoder 38 decodes the n-bit discrete value outputted from the counter 37 so as to generate a (2.sup.n -1) decode signal and supplies it to the variable resistor circuit 36 so as to control the resistance stepwise by 0 to (2.sup.n -1)r.
FIG. 11 further concretely shows the circuit shown in FIG. 10 and is a circuit structural example of the case wherein m=2, n=4. In this circuit shown in FIG. 11, the multibit digital signal is inputted to the sigma-delta modulator 11 and the zero detect circuit 26. A 1-bit output signal NRZ of this sigma-delta modulator 11 is supplied to one side input terminal of the AND gate 12 and is inverted to be supplied to one side input terminal of the NAND gate 13. A clock signal CK1 is supplied to the other side input terminal of the AND gate 12, and the clock signal CK1 is supplied to the other side input terminal of the NAND gate 13.
The output signal RZ of the AND gate 12 is supplied to one end of the resistor 15 via the inverter 14, and the output signal RZn of the NAND gate 13 is supplied to one end of the resistor 17 via the inverter 16. The other ends of the resistors 15, 17 are connected to one end of the resistor 18, and the other end of the resistor 18 is connected to one end of the resistor 19. The capacitor 20 is connected between the one end of the resistor 18 and ground point GND, and the capacitor 21 is connected between the other end of the resistor 18 and ground point GND.
The other end of the resistor 19 is connected to the inverting input terminal (-) of the op-amp 22, and the reference potential VREF is applied to the non-inverting input terminal (+) of this op-amp 22. The reference potential VREF is generated by the resistors 33, 34 connected in series between the power supply VDD and ground point GND and the capacitor 35 connected between the node of these resistors 33, 34 and ground point GND.
The capacitor 23 and the variable resistor circuit 36 are connected in parallel between the output terminal and the inverting input terminal (-) of the op-amp 22 so that the output signal PRZ is feedback to the inverting input terminal (-). In the variable resistor circuit 36, the resistance changes stepwise 0 to 15r by r.
An output signal ZD of the zero detect circuit 26 is supplied to an input terminal U/Di of the 4-bit up/down (U/D) counter 37. A clock signal CK2 is supplied to a clock input terminal CK of the counter 37. Four-bit discrete values outputted from output terminals Q1 to Q4 of the counter 37 are supplied to the decoder 38. This decoder 38 decodes the 4-bit discrete values outputted from the output terminals Q1 to Q4 of the counter 37 so as to generate switch control signals S1 to S15 and supplies these to the variable resistor circuit 36 to control it so that the resistance changes stepwise 0 to 15r by r.
FIG. 12 shows a structural example of the zero detect circuit 26 in the circuit shown in FIG. 11. This zero detect circuit 26 is composed of an OR gate 40, a flip-flop 41, an N-bit counter 42, and a RS flip-flop 43.
The multibit digital signal is supplied to the OR gate 40, and the output of this OR gate 40 is supplied to a data input terminal D of the flip-flop 41. The clock signal CK2 is supplied to a clock input terminal CK of the flip-flop 41, and the output terminal Q is connected to the reset input terminal R of the n-bit counter 42 and the reset input terminal R of the RS flip-flop 43, respectively. The clock signal CK2 is supplied to the input terminal CK of the n-bit counter 41 so that counting operation is performed in response to this clock signal CK2. The most significant bit MSB of this counter 42 is connected to the set input terminal S of the RS flip-flop 43, and a signal ZD is outputted from the output terminal Q of this RS flip-flop 43.
In the zero detect circuit 26, the counting operation is started in the n-bit counter 42 when the multibit digital signal becomes zero data, and the RS flip-flop 43 is set when counting is proceeded to the most significant bit of the counter 42, that is, when zero data are inputted continuously for a predetermined period of time so that the detect signal ZD for zero data is outputted from the output terminal Q of the RS flip-flop 43.
FIG. 13 is a block diagram extracting and showing the 4-bit up/down counter 37 and the decoder 38 in the circuit shown in FIG. 11. The counter 37 is provided with a clock input terminal CKUDi, an input terminal U/Di to which the detect signal ZD for the zero data is supplied, and the output terminals Q1 to Q4.
The output signals Q1, Q2, Q3, Q4 of the 4-bit up/down counter 37 and a strobe signal STROBE are supplied to the decoder 38 which decodes these signals and outputs 15-bit switch control signals SI to S15 for stepwise controlling the resistance Rmt of the variable resistor circuit 36.
FIG. 14 is a circuit diagram showing a concrete structural example of the 4-bit up/down counter 37 shown in FIG. 13. This counter 37 is composed of flip-flops 44 to 51, inverters 52, 53, NAND gates 54, 55, a NOR gate 56, exclusive NOR gates 57 to 60, exclusive OR gates 61 to 63, and the like.
Clock input terminals CK of the flip-flops 44, 45 are connected to the input terminal CKUDi. The data input terminal D of the flip-flop 50 is connected to the input terminal U/Di. The data output terminal Q of the flip-flop 44, the data input terminal D of the flip-flop 45, and the clock input terminals CK of the flip-flops 46, 50, 51 are connected to a terminal CKUD, respectively. Here, a signal of the terminal CKUD is inverted and supplied to the clock input terminals CK of the flip-flops 50, 51. The signal of this terminal CKUD becomes a clock signal of the period of 4 times the clock signal supplied to the input terminal CKUDi.
The output terminal of the inverter 52 and the first input terminal of the NAND gate 55 are connected to the data input terminal D of the flip-flop 44. The data output terminal Q of the flip-flop 45 is connected to the input terminal of the inverter 52, and a signal HOLD is supplied thereto. The output terminal of the NAND gate 55 is connected to one side input terminals of the exclusive NOR gates 57 to 60, respectively, and a signal HOLD' is supplied thereto. The output terminals of the exclusive NOR gates 57 to 60 are connected to the data input terminals D of the flip-flops 46 to 49, respectively.
The output terminal Q of the flip-flop 46 is connected to the other side input terminal of the exclusive NOR gate 57, the output terminal Q1, the first input terminal of the NAND gate 54, the first input terminal of the NOR gate 56, and one side input terminal of the exclusive OR gate 61, respectively.
The output terminal Q of the flip-flop 47 is connected to the other side input terminal of the exclusive NOR gate 58, the output terminal Q2, the second input terminal of the NAND gate 54, the second input terminal of the NOR gate 56, and one side input terminal of the exclusive OR gate 62, respectively. The output terminal of the exclusive OR gate 61 is connected to the clock input terminal CK of the flip-flop 47 so as to provide a signal Q1' thereto.
The output terminal Q of the flip-flop 48 is connected to the other side input terminal of the exclusive NOR gate 59, the output terminal Q3, the third input terminal of the NAND gate 54, the third input terminal of the NOR gate 56, and one side input terminal of the exclusive OR gate 63, respectively. The output terminal of the exclusive OR gate 62 is connected to the clock input terminal CK of the flip-flop 48 so as to provide a signal Q2' thereto.
The output terminal Q of the flip-flop 49 is connected to the other side input terminal of the exclusive NOR gate 60, the output terminal Q4, the fourth input terminal of the NAND gate 54, and the fourth input terminal of the NOR gate 56, respectively. The output terminal of the exclusive OR gate 63 is connected to the clock input terminal CK of the flip-flop 49 so as to provide a signal Q3' thereto.
The data output terminal Q of the flip-flop 50 is connected to the data input terminal D of the flip-flop 51. The data output terminal Q of this flip-flop 51 is connected to the fifth input terminal of the NAND gate 54, the fifth input terminal of the NOR gate 56, and the other side input terminals of the exclusive OR gates 61, 62, 63, respectively, so as to provide a signal U/D thereto, respectively.
Further, the output terminal of the NAND gate 54 is connected to the second input terminal of the NAND gate 55 so as to provide a signal ALL1/ ("/" added after the numeral means a inverted signal, that is, a bar). The output terminal of the NOR gate 56 is connected to the input terminal of the inverter 53, and the output terminal of this inverter 53 is connected to the third input terminal of the NAND gate 55 so as to provide a signal ALL0 thereto.
Respective FIGS. 15A, 15B, and 15C show structural examples of the decoder 38 in the circuit shown in FIG. 13. FIG. 15A is a concrete circuit diagram, FIG. 15B is a symbol diagram of the shift register in FIG. 15A, and FIG. 15C is a circuit diagram showing a detailed structural example of a shift register shown in FIG. 15B.
The decoder 38 is composed of AND gates 71 to 78, inverters 79 to 86, NAND gates 87 to 101, and shift registers 102 to 116. The count output Q1 of the up/down counter 37 is supplied to the input terminal of the inverter 79 and is inverted so as to be supplied to one side input terminals of the AND gates 71, 73. The count output Q2 is supplied to the input terminal of the inverter 80 and is inverted so as to be supplied to the other side input terminal of the AND gate 71 and one side input terminal of the AND gate 72. The count output Q3 is supplied to the input terminal of the inverter 81 and is inverted so as to be supplied to one side input terminals of the AND gates 75, 77. Further, the count output Q4 is supplied to the input terminal of the inverter 82 and is inverted so as to be supplied to the other side input terminal of the AND gate 75 and one side input terminal of the AND gate 76.
The output signal of the inverter 79, after being inverted, is supplied to the other side input terminal of the AND gate 72 and, after being inverted, is supplied to one side input terminal of the AND gate 74. The output signal of the inverter 80, after being inverted, is supplied to the other side input terminal of the AND gate 73 and, after being inverted, is supplied to the other side input terminal of the AND gate 74. The output signal of the inverter 81, after being inverted, is supplied to the other side input terminal of the AND gate 76 and, after being inverted, is supplied to one side input terminal of the AND gate 78. The output signal of the inverter 82, after being inverted, is supplied to the other side input terminals of the AND gates 77, 78.
When the count outputs Q1, Q2, Q3, Q4 of the counter 37 are put as A, B, C, D, respectively, the logical output of the AND gate 71 becomes A/*B/, the logical output of the AND gate 72 becomes A*B/, the logical output of the AND gate 73 becomes A/*B, the logical output of the AND gate 74 becomes A*B, the logical output of the AND gate 75 becomes C/*D/, the logical output of the AND gate 76 becomes C*D/, the logical output of the AND gate 77 becomes C/*D, and the logical output of the AND gate 78 becomes C*D.
Here, "/" added after a symbol means a bar, and A/, B/, C/, and D/ mean the inverted signals of A, B, C, and D, respectively.
The output signal of the AND gate 71 is supplied to one side input terminals of the NAND gates 90, 94, 98, respectively, and the output signal of the AND gate 72 is supplied to one side input terminals of the NAND gates 87, 91, 95, 99, respectively. The output signal of the AND gate 73 is supplied to one side input terminals of the NAND gates 88, 92, 96, 100, respectively, and the output signal of the AND gate 74 is supplied to one side input terminals of the NAND gates 89, 93, 97, 101, respectively. The output signal of the AND gate 75 is supplied to the other side input terminals of the NAND gates 87 to 89. The output signal of the AND gate 76 is supplied to the other side input terminals of the NAND gates 90 to 93. The output signal of the AND gate 77 is supplied to the other side input terminals of the NAND gates 94 to 97. Further, the output signal of the AND gate 78 is supplied to the other side input terminals of the NAND gates 98 to 101. The output signals of the NAND gates 87 to 101, after being inverted, are supplied to the data input terminals of the shift registers 102 to 116, respectively.
The strobe signal STROBE is supplied to the clock input terminals CK of the respective shift registers 103, 105, 107, 109, 111, 113, 115 via the inverters 83 to 85, and the strobe signal STROBE is supplied to the clock input terminals CK of the respective shift registers 102, 104, 106, 108, 110, 112, 114, 116 via the inverters 83, 84, 86. The switch control signals S1 to S15 are outputted from the output terminals Q of the respective shift registers 102 to 116.
The shift registers 103 to 116 shown by a symbol diagram of FIG. 15B are constituted as shown in FIG. 15C, respectively. That is, each of the sift registers 103 to 116 is composed of clocked inverters 120, 121 controlled by a clock signal .phi./ (a signal of an opposite phase to a clock signal .phi.), clocked inverters 122, 123 controlled by the clock signal .phi., and inverters 124, 125. In the clocked inverter 120, the inverter 124, the clocked inverter 123, and the inverter 125, their output terminals and the input terminals are sequentially connected in cascade. The input terminal of the clocked inverter 122 is connected to the output terminal of the inverter 124, and the output terminal thereof is connected to the input terminal of this inverter 124. The input terminal of the clocked inverter 121 is connected to the output terminal of the inverter 125, and the output terminal thereof is connected to the input terminal of this inverter 125. The structure is constituted so that the inputted data are taken after the data are inverted in the inverter 126.
FIG. 16 is a truth table for explaining about operations of the decoder 38 shown in FIG. 11 and shows logical operations of the circuit shown in FIG. 15A all together. The switch control signals S1 to S15 selectively go to "H" level in accordance with combinations of the levels of the input signals A, B, C, D, and the variable resistor circuit 36 is controlled so that its resistance changes 15r to 0. For example, when the input signals A, B, C, D are all at "0" level, the resistance Rmt of the variable resistor circuit 36 becomes the maximum resistance 15r (attenuation level=15/15). When the input signal A is at "1" level and the input signals B, C, D are at "0" level, the switch control signal S1 goes to "H" level and attenuation level=14/15. As the following, similarly, attenuation level decreases for each 1/15 in accordance with the levels of the input signals, and when the input signals A, B, C, D all become "1" level, the switch control signal S15 becomes "H" level, and the resistance Rmt of the variable resistor circuit 36 becomes the minimum resistance 0 (attenuation level=0/15).
Respective FIGS. 17A, 17B, and 17C show a concrete structural example of the variable resistor circuit (feedback resistor) 36 in the circuit shown in FIG. 11. FIG. 17A is the entire circuit diagram, FIG. 17B is a symbol diagram of an analog switch circuit in the circuit shown in FIG. 17A, and FIG. 17C is a circuit diagram showing a detailed structural example of the analog switch circuit shown in FIG. 17B.
This variable resistor circuit 36 is composed of resistors R1 to R15 wherein each resistance is r and analog switch circuits SW1 to SW15. The resistors R1 to R15 are connected in series between the inverting input terminal (-) and the output terminal of the op-amp 22. The current paths of the analog switch circuits SW1 to SW15 are connected between the nodes of the resistors R1 to R15 and the inverting input terminal (-) of the op-amp 19, respectively. The switch control signals SI to S15 outputted from the decoder 38 are supplied to the analog switch circuits SW1 to SW15 so as to selectively perform on/off control. With this, the feedback resistor of the op-amp 22 changes stepwise 0 to 15r by resistance r, and the DC displacement by the mute on/off moves on smoothly as shown in FIG. 8 to reduce the click sound.
The respective analog switch circuits SW1 to SW15 shown in the symbol diagram of FIG. 17B are constituted of P channel MOS transistors P1, P2, P3, N channel MOS transistors N1, N2, and an inverter INV1, for example, as shown in FIG. 17C. The current paths of the MOS transistors P1 and N1 are connected in parallel, and the current paths of the MOS transistors P2 and N2 are connected in parallel. The current paths of the MOS transistors P1, N1 are connected between a terminal I and a terminal O of the analog switch circuit SW.
A terminal C of the analog switch circuit SW is connected to the input terminal of the inverter INV1, and the output terminal of this inverter INV1 is connected to the gates of the MOS transistors P1, P2. One end of the current paths of the MOS transistors N2, P2 is connected to the back gate of the MOS transistor P1, and the other end is connected to the terminal O. The current path of the MOS transistor P3 is connected between the back gate of the MOS transistor P1 and the power supply VDD, and the gate of this MOS transistor P3 is connected to the gates of the MOS transistors N1, N2 and the terminal C. The back gates of the MOS transistors N1, N2 are connected to ground point GND, and the back gates of the MOS transistors P2, P3 are connected to the power supply VDD.
The analog switch circuit shown in FIG. 17C has a characteristic that the on resistance is small.
Respective FIGS. 18 and 19 are timing charts for explaining the operations of the circuits shown in FIGS. 11 to 17C. Here, the operations of the zero detect mute circuit 26 and the 4-bit up/down counter 37 are mainly paid attention.
First, when the up/down counter 37 is in 0 state, the resistance Rmt of the variable resistor circuit 36 is 15r, being in normal state.
When the input to the DAC is zero data for a constant period of time, the output signal ZD of the zero detect circuit 26 goes to "H" level, that is, the input terminal U/Di of the up/down counter 37 becomes "H" level. When the input terminal U/Di becomes "H" level, this counter 37 starts the up-count operation so that the discrete value of the counter 37 increases as 1, 2, 3, . . . , in a count up condition. In accordance with this, the switch control signals S1, S2, S3, . . . of the decoder 38 sequentially go to "H" level, and the analog switch circuits SW1, SW2, SW3, . . . responding thereto are sequentially turned on so that the resistance Rmt of the variable resistor circuit 36 becomes smaller as 14r, 13r, 12r, . . . . Then, finally, the switch control signal S15 goes to "H" level, and the variable resistor circuit 36 goes to a short-circuited condition (the condition of the counter is 15) to be the mute ON.
Conversely, when the DAC input is not zero data any more, the signal ZD immediately goes to "L" level, that is, the input terminal U/Di of the up/down counter 37 becomes "L" level. When the input terminal U/Di becomes "L" level, the up/down counter 37 starts the down-count operation so that the discrete value of the counter 37 decreases as 14, 13, 12, . . . . In accordance with this, the switch control signals S14, S13, S12, . . . outputted from the decoder 38 sequentially go to "H" level, and the analog switch circuits SW14, SW13, SW12, responding thereto are sequentially turned on so that the resistance Rmt of the variable resistor circuit 36 becomes greater as r, 2r, 3r, . . . . Then, finally, the discrete value of the counter 37 becomes 0, and all analog switch circuits SW1 to SW15 become the oft state. Thus, the resistance Rmt of the variable resistor circuit 36 becomes 15r of the normal time so as to be the mute off.
As shown in a period T1 of FIG. 19, when the number of continuous zero data is small and the DAC input is not zero data any more before the discrete value of the counter 37 reaches 15, from that point, the down count operation is performed. Since the state becomes from a fade-out state to a fade-in state, it does not become the mute ON.
As shown in a period T2, after the period where the number of continuous zero data is small and the DAC input is not zero data any more before the discrete value of the counter 37 reaches 15 so that the down count operation is performed, when zero data are detected again, the state repeats from a fade-out state to a fade-in state, and to the fade-out state.
FIG. 20 is a circuit diagram showing a structural example of a mute circuit of the case in which a filter amplifier section of the DAC is a differential amplifier type. In this case, not only the feedback resistor but also the resistance between the non-inverting input terminal (+) and the reference potential (VREF) are needed t o b e changed.
In the circuit shown in FIG. 20, like reference numerals are attached to like structural sections that are similar to those in FIG. 10, and detailed explanation are omitted therefor. That is, the first analog output of an m level DAC 31' is supplied to the inverting input terminal (-) of the op-amp 22 via resistors 32-1, 18-1, 19-1, and the second analog output (the inverted one of the first analog output) is supplied to the non-inverting input terminal (+) of the op-amp 22 via resistors 32-2, 18-2, 19-2. One side electrode of the capacitor 20 is connected to the node between the resistors 32-1 and 18-1, and the other electrode is connected to the node between the resistors 32-2 and 18-2. One side electrode of the capacitor 21 is connected to the node between the resistors 18-1 and 19-1, and the other electrode is connected to the node between the resistors 18-2 and 19-2.
A variable resistor circuit 39 is provided at the non-inverting input terminal (+) of the op-amp 22, and the resistance Rmt is stepwise controlled by 0 to (2.sup.n -1)r for each resistance r by means of the output signal of the decoder 38.
FIG. 21 is a circuit diagram (m=2, n=4) showing a concrete example of the circuit shown in FIG. 20. The output signal RZ of the AND gate 12 is supplied to the input terminal of an inverter 14-1 as well as the input terminal of an inverter 14-2 via an inverter 10-1. The output signal RZn of the NAND gate 13 is supplied to the input terminal of an inverter 16-1 as well as the input terminal of an inverter 16-2 via an inverter 10-2. The output terminals of the inverters 14-1, 16-1, 14-2, 16-2 are connected to one ends of resistors 15-1, 17-1, 15-2, 17-2, respectively. The other ends of the resistors 15-1, 17-1 are connected with each other so as to be connected to one end of the resistor 18-1, and the other ends of the resistors 15-2, 17-2 are connected to each other so as to be connected to one end of the resistor 18-2.
In order to reduce the click sound as much as possible, it is necessary to further smoothen the waveform at the time of the mute on/off as being obvious from the comparison of FIG. 8 and FIG. 9.
Here, it will be considered to double the change step number of the feedback resistor (the variable resistor circuit 36 shown in FIG. 17A) of the op-amp 22 in the circuit shown in FIGS. 10 and 11.
FIG. 22 is a circuit diagram showing a structural example of a variable resistor circuit 36' in which the change step number is doubled. As shown in the drawing, needed are 31 resistors connected in series between terminals IN and OUT, one analog switch circuit connected between the terminals IN and OUT, and 30 analog switch circuits connected between the nodes of the respective resistors and the terminal OUT. That is, it is obvious that the circuit scale is doubled.
FIG. 23A is a symbol diagram of an analog switch circuit in the circuit shown in FIG. 22, and FIG. 23B is a circuit diagram showing the detailed structural example thereof. This analog switch circuit is composed of a P channel MOS transistor P4 and an N channel MOS transistor N4 whose current paths are connected in parallel between the terminal I and the terminal O, and an inverter INV2. The input terminal of the inverter INV2 is connected to the terminal C, and the output terminal thereof is connected to the gate of the MOS transistor P4. The back gate of this MOS transistor P4 is connected to the power supply VDD, and the back gate of the MOS transistor N4 is connected to ground point GND.
Even if this type of analog switch circuit with a relatively small number of elements is employed, when the change step number of the resistance is tried to be increased, a drastic increase in the circuit scale cannot be avoided.
Further, a decoder 38' supplying the switch control signals S1 to S31 to the analog switch circuits shown in FIGS. 22, 23A, and 23B becomes large scaled as shown in FIGS. 24, 25A, 25B, and 25C to be approximately doubled in the circuit scale.
FIG. 26 shows the relationship between input signals A, B, C, D, E and the switch choosing signals S1 to S31 in the decoder 38' shown in FIG. 25A and truth table of states of the mute circuit.
In FIGS. 25A, 25B, and 25C, although shift registers in the circuit shown in FIGS. 15A, 15B, and 15C are constituted with a latch circuit with a small number of elements, the circuit scale is drastically increased.
Albeit the circuit scale of the up/down counter 37' does not become so large, since the circuit scales of the feedback resistor 36' and the decoder 38' become doubled, the entire circuit scale becomes considerably large.
Moreover, when the step number is quadrupled, the circuit scales of the feedback resistor and the decoder are quadrupled, thereby increasing the load immensely. When a filter amplifier section of a DAC is a differential amplifier type, since it is necessary to constitute similarly not only the feedback resistor of the op-amp but also the resistor between the non-inverting input terminal and the reference potential, the circuit scale is further increased.
As described above, there is a problem in a conventional variable resistor circuit wherein an increase in the step number causes an increase in the circuit scale.
Further, in a D/A converter in which the variable resistor circuit is employed as a feedback resistor, there is a problem wherein when the step number of the feedback resistor is increased in order to reduce the click sound, the circuit scales of the feedback resistor and the decoder become immensely large, thereby engendering a cause bringing about a cost increase.